Re: AGP question -> DIMM - Chipset compatibility

[NZG <ngustavson@emacinc.com>]

> Actually, that is an addressing issue, hence a technology/IC size issue,
> in combination with the IC width.
> Again, DRAM cell refresh doesn't have anything to do with it.
Refreshing aside, correct me if I'm wrong, but for a controller(chipset or 
otherwise)  to address a block of dram it uses it's address lines to latch a 
row/column to the DRAM. This is what I'm talking about. 
Different memory controllers can handle different numbers of columns and rows.
I think you actually allude to this later in your discussion.
I agree DRAM refresh has nothing to do with it.

>
> BTW, ICs are not always parallel.
> Sometimes there is more than two 32-bit banks in a single DIMM,
> and buffering is used.
This may be true, in my realm I never see DRAM address lines that are not 
however.(at least not on one DIMM)

>
> > These are still typically called data lines, just data lines from the
> > memory controller, rather than the PCI bus.
>
> Not true.
If you look at page 32 of the intel registered DIMM specification, it refers 
to lines DQ[63:0] as being in the "Data" group. It then goes on to refer to 
them at several points as being "data lines"

> Memory banking has 0 to do with the "front side bus" of a CPU (I see you
> are making this assumption based on your next statement below)..

> > What I've seen is that some of the older 486 processors will only have
> > 32 (memory) data lines for DRAM.
I agree my terminology here was sloppy, I was referring to the memory 
controller, which in a microprocessor based system does typically reside on 
the chipset, yes. Most processors I work with have only 1 or 2 options for 
the chipset, and they typically have about the same memory controller built 
in them. Indeed, I often work with microcontrollers, which do have the memory 
controller built into the same IC as the processor.
Hence I rarely need to make the distiction.

> Not width of the IC.
> Typically that is hard-traced.
> It's the total IC tech/size and addressing that might not be supported.
> Don't confuses address lines with data lines.
I'm not confusing them, I'm just commenting on how they come into play, and 
can result in less available memory if they are not routed correctly.
Many 32 bit wide memory controllers route their DQ/DQM/bank selects in strange 
patterns to maximize the width they can get from the IC.
I do acknowlege that this might not have anything to do with the difference 
between these two specific chipsets however.

NZG.


NZG.

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