Re: AGP question -> DIMM - Chipset compatibility

["Bryan J.Smith" <b.j.smith@ieee.org>]

NZG wrote:
> True, but each individual IC may have more columns than the controller can
> reach, which would result in less memory being seen by the device overall.

Actually, that is an addressing issue, hence a technology/IC size issue, 
in combination with the IC width.
Again, DRAM cell refresh doesn't have anything to do with it.

> The DRAM modules are made up of individual IC's, but typically they are all
> connected to the address bus in parallel. If the address bus cannot see all
> of a single IC, it cannot see all of any of the IC's and will have memory
> that will show up as a smaller size than it actually is.(half, 1/4th, 
> etc...)

Again, that's the address/IC tech.  Since ICs must match, then yes, they 
all are affected.
But row, column, etc...  DRAM cell refresh and timing has nothing to do 
with that.

BTW, ICs are not always parallel.
Sometimes there is more than two 32-bit banks in a single DIMM,
and buffering is used.

> These are still typically called data lines, just data lines from the 
> memory controller, rather than the PCI bus.

Not true.

Memory banking has 0 to do with the "front side bus" of a CPU (I see you 
are making this assumption based on your next statement below)..
In fact, except for AMD64, all memory channels are converted into 
variable-size widths to the CPU(s) (depending on chipset/CPU).

Intel still does not have a true system interconnect, and uses variants 
of its 14-year old PC/AT compatible 32-bit addressable (PAE36/64GiB), 
64-bit wide GTL bus.
It has created burst implementations in AGTL+ and other forms that are 
actually not 64-bit.
And *all* are "3-port shared hub."
Intel will "widen" the hub for more throughput on servers.
The MCH is how the "front-side bus" interfaces with the memory, and has 
0 to do with the CPU itself.

That's why Socket-478 is really still a *single* DDR capable CPU - it's 
still a single 64-bit GTL bus to/from the CPU
(S603/604 *does* have a true 128-bit path though).
Same deal with so-called Socket-462 "dual-DDR" - the CPU is *still* a 
*single* 64-bit EV6 connection.

AMD abandoned GTL after the K6.
It now uses 40-bit addressable, 64-bit wide EV6 (Alpha 264).
It's predecessor, EV56 (Alpha 164A), was actually 128-bit, but a "shared 
hub" like Intel.
EV6 is designed to be an up to 16-port "crossbar switch."
You can use however many "64-bit ports" for whatever you want.
Athlon MP used 1 independent ports for each CPU, then 1 for memory and 1 
for I/O.
Some Alpha 264 systems had 8 x 4 x 4 (CPU x Memory x I/O).

Opteron no longer uses EV6 for interconnect, although it's current 
NUMA/HyperTransport still uses EV6 40-bit addressing for compatibility 
(even the original Athlon 32 was 40-bit capable).
There is either a *direct* 1 x 184-pin DDR channel (S754) or 2 x 184-pin 
DDR channels (S939/940).
If you've been wondering why there's the difference, it's simple 
addition:  754 + 184 equals 938.
The memory is 100 percent "glueless" - pin-to-pin, no "memory controller 
hub" to/from GTL or "crossbar switch" to/from EV6.

For I/O, HyperTransport is a virtualized system bus of variable width - 
from 1+1 to 32+32.
Yes, HT only allows up to 32-bit in one direction.
It then allows up to 2000MT (meta-transactions).
S940 processors have upto 3 of them, at far less pin-count than a DDR 
channel
(which is why HyperTransport is the "holy grail" for engineers who 
design platforms).
Now there is nothing stopping anyone from putting a HyperTranport memory 
controller.
In fact, this is what PowerPC 970 / Apple G5 does.
But AMD64 CPUs will use memory attached to other CPUs over their direct 
or indirect HyperTransport links.

> What I've seen is that some of the older 486 processors will only have 
> 32 (memory) data lines for DRAM.

You are confusing "logical" datapath with "physical."
And you are not distinguishing between CPU and chipset.

Yes, GTL is *logically* 64-bit, and a "hub" architecture.
But Intel can widen it to 128-bit or 256-bit.
But that has 0 to do with DDR channel memory addressing.
EV6 is both logically and physically a 64-bit "switch" of up to 
16-ports.

Only AMD64 actually has direct DDR channels - direct paths - direct 
control, pin for pin.

> With DIMMs you can see all the memory by
> playing games with how the data lines of the chipset line up with the data
> lines of the DIMM, and using the mask bits/bank selects to split the 64 bit
> bus into 2 sides with 32 bit access.

Yes, on the DIMM and memory controller.
And yes, up to the chipset or other "glue" logic that converts it.
Also note you can have 4 x 32-bit banks on a single 64-bit DIMM.

That's also why the same Socket-370 processor can take *different* IC 
tech, size, width and numbers based on chipset.
So the CPU has 0 to do with memory compatibility - except for AMD64.

> A problem arises with the SODIMM architecture, which forces a 64 bit 
> wide data
> bus, and typically results in the older 32 bit controllers only seeing half
> of the memory (unless you get really fancy with a PLD or something).

That's different.
You're continuing to introduce concepts outside the basic one I'm 
having.
And mine was simple.
And that's how the exact same processor can have different memory 
requirements.

> I kind of figured that this is a similar situation. The way the data
> lines/mask bits/bank selects line up, don't allow the entire width of 
> the individual IC's to be seen.

Not width of the IC.
Typically that is hard-traced.
It's the total IC tech/size and addressing that might not be supported.
Don't confuses address lines with data lines.

> Yes, that may be true, but I think this is an oversimplification.

Of course it is an over simplification.
I'm not going to get into chip selects, tri-state buffers and diagram 
the logic differences (and resulting support differences) between the 
i440BX and i810/815.

> Your just saying that the DIMMs can't be seen because the Chipset can't see
> them, which doesn't really tell you anything.

I'm saying the chipset cannot address the full size of each, individual 
DIMM.
Memory controllers are exact in their pin-outs, MEAGs (one-hots) and 
other traces.
They cannot be "arbitrarily programmed".

> The question is, why is that from a physical layout standpoint.
> The answer is probably address/data/bank select lines correct?

Yes.  Exactly.

--
Bryan J. Smith   mailto:b.j.smith@ieee.org
Currently Mobile

-
To unsubscribe, send email to majordomo@silug.org with
"unsubscribe silug-discuss" in the body.