Re: AGP question -> DIMM - Chipset compatibility

["Bryan J.Smith" <b.j.smith@ieee.org>]

NZG wrote:
> This may be true, in my realm I never see DRAM address lines that are 
> not however.(at least not on one DIMM)

Sure you have.
32/36 IC x4-bit and Even 16/18 IC x8-bit Buffered/Registered are all 
over.
That's 128-bits of aggregate IC data paths on a single DIMM.

> If you look at page 32 of the intel registered DIMM specification, it 
> refers
> to lines DQ[63:0] as being in the "Data" group. It then goes on to refer to
> them at several points as being "data lines"

That's the DIMM itself, yes, I never disagreed.
What I was talking about was whether or not it was physically (and not 
logically) 64-bit at the CPU.
Many people assume the CPU and its interconnect is always a 64-bit 
datapath,
and the CPU somehow defines memory compatibility/requirements.
Your comments about the i486 suggested to me that you were not 
differentiating.

> I agree my terminology here was sloppy, I was referring to the memory
> controller, which in a microprocessor based system does typically reside on
> the chipset, yes. Most processors I work with have only 1 or 2 options for
> the chipset, and they typically have about the same memory controller built
> in them.


Now that statement is utterly false.
Intel regularly builds memory controllers that are completely different 
for the same CPUs.

AMD, on the other hand, has always been a bit more flexible in its 
chipset memory compatibility.

>  Indeed, I often work with microcontrollers, which do have the memory
> controller built into the same IC as the processor.

And you may possibly be using SRAM and not DRAM as well?

> Hence I rarely need to make the distiction.

It's a world of difference in the "front-side bottleneck" of the PC 
world.
But still, I'll give you credit, you know a crapload more than most 
anyone.

What enfuriates me is when I get crossed by people who don't know 
anything but PCxxx-whatever branding.
Synchronous timing doesn't even touch the tip of the iceberg when it 
comes to memory compatibility.

> I'm not confusing them, I'm just commenting on how they come into play, and
> can result in less available memory if they are not routed correctly.
> Many 32 bit wide memory controllers route their DQ/DQM/bank selects in 
> strange
> patterns to maximize the width they can get from the IC.

Okay, I get what you are saying now.

> I do acknowlege that this might not have anything to do with the difference
> between these two specific chipsets however.

Right.
I went off on tangents as well.

Again, you're not the type of person I have to worry about saying,"But 
it's PC133" or "PC3200, why doesn't it work?"
--
Bryan J. Smith   mailto:b.j.smith@ieee.org
Currently Mobile

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