Re: AGP question -> DIMM - Chipset compatibility

[NZG <ngustavson@emacinc.com>]

> Er, the row/column nomenclature is typically referring to the DRAM cells
> individually when it comes to timing.
> Think bigger, like the fact that DRAM "modules" are made up of
> individual ICs.
True, but each individual IC may have more columns than the controller can 
reach, which would result in less memory being seen by the device overall.
The DRAM modules are made up of individual IC's, but typically they are all 
connected to the address bus in parallel. If the address bus cannot see all 
of a single IC, it cannot see all of any of the IC's and will have memory 
that will show up as a smaller size than it actually is.(half, 1/4th, etc...)


> The PC bus doesn't matter, especially since Intel's FSB connects into
> its "Memory Controller Hub" (MCH) and memory connects directly to 1 or 2
> DDR channels on AMD EV6/NUMA (A64/Opteron) processors.

These are still typically called data lines, just data lines from the memory 
controller, rather than the PCI bus.

What I've seen is that some of the older 486 processors will only have 32 
(memory) data lines for DRAM. With DIMMs you can see all the memory by 
playing games with how the data lines of the chipset line up with the data 
lines of the DIMM, and using the mask bits/bank selects to split the 64 bit 
bus into 2 sides with 32 bit access.

A problem arises with the SODIMM architecture, which forces a 64 bit wide data 
bus, and typically results in the older 32 bit controllers only seeing half 
of the memory (unless you get really fancy with a PLD or something).

I kind of figured that this is a similar situation. The way the data 
lines/mask bits/bank selects line up, don't allow the entire width of the 
individual IC's to be seen.


> Today's DIMMs are 2 x 32-bit banks, or 64-bit (2x36, or 72 for ECC).
> *However*, the actual "aggregate bit width" of all ICs on a DIMM can
> actually be a multiple.
> That throws even more wrenches into the equation.  :-)
>
> > 3. Differnet number of bank selects(which is really the same thing as 1.)
>
> Bank selects of the memory controller?
> Or on the DIMM itself?
Either, the problem would come in when they don't match up.

> Chipsets *only" support specific IC technologies, widths and
> combinations.
> The i440BX only supported 256MB DIMMs that used 16Mb*4-bit ICs (128M
> tech) in 32/36 chip configurations - which results in a Registered DIMM
> (128-bit aggregate width, 64-bit DIMM).
> The i810/815 only support 256MB modules that are 8-bit or 16-bit (4 or 8
> chip, 64-bit aggregate), with increasing IC technology (256M, 512M,
> 1024M).
Yes, that may be true, but I think this is an oversimplification.
Your just saying that the DIMMs can't be seen because the Chipset can't see 
them, which doesn't really tell you anything.
 The question is, why is that from a physical layout standpoint.
The answer is probably address/data/bank select lines correct?


NZG.

-
To unsubscribe, send email to majordomo@silug.org with
"unsubscribe silug-discuss" in the body.