Re: AGP question --Bryan and Aaron- Thanks!

["Bryan J.Smith" <b.j.smith@ieee.org>]

NZG wrote:
> I'll take a stab at that, although I'm not really fluent on the 
> specifics of
> those chipsets I'd say it's either..
> 1. Different number of address lines (or different maximum columns)

Er, the row/column nomenclature is typically referring to the DRAM cells 
individually when it comes to timing.
Think bigger, like the fact that DRAM "modules" are made up of 
individual ICs.

> 2. Different number of data lines? Although I'm not sure this applies 
> in the non-embedded realm. Do all modern PC's have 64 bit data bus's?

The PC bus doesn't matter, especially since Intel's FSB connects into 
its "Memory Controller Hub" (MCH) and memory connects directly to 1 or 2 
DDR channels on AMD EV6/NUMA (A64/Opteron) processors.

Today's DIMMs are 2 x 32-bit banks, or 64-bit (2x36, or 72 for ECC).
*However*, the actual "aggregate bit width" of all ICs on a DIMM can 
actually be a multiple.
That throws even more wrenches into the equation.  :-)

> 3. Differnet number of bank selects(which is really the same thing as 1.)

Bank selects of the memory controller?
Or on the DIMM itself?

> Did I come close?

In a nutshell, to over-simplify things, there are 3 factors:
- IC Technology (128M, 256M, 512Mm etc... - maps to 16Mb, 32Mb, 64Mb, 
etc... ICs)
- IC Width (4-bit, 8-bit, 16-bit, 32-bit)
- Resulting aggregate IC number and width (typically 64/72 or 128/144 - 
the latter is commonly "Registered," but not always).

Chipsets *only" support specific IC technologies, widths and 
combinations.
The i440BX only supported 256MB DIMMs that used 16Mb*4-bit ICs (128M 
tech) in 32/36 chip configurations - which results in a Registered DIMM 
(128-bit aggregate width, 64-bit DIMM).
The i810/815 only support 256MB modules that are 8-bit or 16-bit (4 or 8 
chip, 64-bit aggregate), with increasing IC technology (256M, 512M, 
1024M).

Putting a 256MB DIMM (32Mb * 8-bit * 8 chip or 64Mb * 16-bit * 4 chip) 
from a i810/815 in a i440BX would not work in many cases, or possibly 
come up as 128MB or 64MB as the i440BX did support 16Mb * 8-bit * 8-chip 
(128MB) or 16Mb * 16-bit * 4-chip (64MB) and the last half or 3/4ths of 
the DRAM cells could not be addressed.

Going the other way, the i440BX's 256Mb module would not work in the 
i810/815.
A "colleague" of mine ignored me and listened to a reseller's comments 
on "high density" and "low density" (ICs?  IC Width?  ???) and ran into 
this exact issue.
He became confused and then took his frustration out on me,
without bothering toread the chipset engineering specification sheets 
from Intel that pointed out everything I was saying.

Basic memory controller design.
The more flexible, exponetially the more gates.
So many are limited in their support, and don't/can't support modules 
before their release.
Now there are additional timing and buffer issues too - but those are 
another story.

--
Bryan J. Smith   mailto:b.j.smith@ieee.org
Currently Mobile

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